Although a background as well as example embodiments of the present invention will be described in connection with an IC testing environment, practice of the invention is not limited thereto, i.e., the invention may be able to be practiced within other environments or for other types of uses.
Dramatic advancements in mixed-signal circuit during the past two decades has led to more stringent requirements and challenge for the mixed signal integrated circuit testing. The increasing testing cost and the difficult in detecting and isolating circuit faults due to the growing integration density and the variety natures of analog faults has been driving the recent development of more sophisticated automatic test equipment (ATE) and testing methodologies. However, one of the first obstacles the ATE testing has to overcome has been the front-end design of the testing equipment, that is how to pick-up the local signal information on the very tiny and sensitive integrated circuit device accurately and transport it safely to the off-chip testing equipment, without disturbing/influencing operation of the sensitive integrated circuit device. Usually signal detection (without disturbing) and conditioning (e.g., amplification, driving) have been the weakest link in the current mixed-signal integrated circuit testing and debugging processes.
More particularly, referencing FIG. 1, illustrated is a schematic diagram of an example system having a disadvantageous non-buffered arrangement for testing sensitive voltages within an integrated circuit (IC) 100. On IC 100, there is shown a miscellaneous circuit portion represented generically by the dashed portion C, and containing, for example, two internal nodes (e.g., probe pads) designated V1 and V2 and allowing access to internal voltages. Further shown, is an interconnection line L providing electrical connection between, for example, the V1 connection point and an output probe pad V0 provided at a periphery of the IC 100, such output probe pad V0 allowing an ATE probe P to be connected thereto without physically contacting the actual sensitive circuit C.
A problem with the FIG. 1 arrangement is that a contemporary circuit C typically operates with very low voltages (e.g., 0.3 V), and thus has very sensitive internal nodes (e.g., V1, V2) which could easily be disturbed in electrical operation thereof by an impedance of the ATE probe. More particularly, it is well known that the ATE probe P has an unavoidable impedance Z associated therewith, and such impedance often is sufficient to disturb voltage levels at the internal node of which the probe is attempting to gain an accurate measurement. For example, a normal operating voltage at an internal node V1 might be 0.18 V, but the impedance influence by a connected ATE probe P might cause an influence thereon an a resultant false reading of 0.21 V.
Accordingly, what is needed is an improved arrangement providing adequate buffering/isolation so as to allow a subject voltage to be accurately made available (e.g., for ATE testing) without a disturbance of the subject voltage. More particularly, needed is an improved arrangement for testing analog or low frequency signal levels within very sensitive internal nodes in mixed-signal integrated circuits.